1. Field of the Invention
The present invention relates to a digital computer and, more particularly, to a data processing device with increased speed due to parallel processing of a plurality of instructions.
2. Description of the Prior Art
The IBM 360/91 exists as an example of a general purpose computer with increased speed due to parallel processing of a plurality of instructions. This computer is disclosed in detail in IBM Journal Jan. 1967, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units". The computer adopts a common data bus system (which will be referred to as a "CDB system") so as to eliminate factors blocking the parallel processing, which are caused by the repeated uses of an identical register between adjoining instructions. According to this system, an instruction having the arithmetic result of a preceding instruction as an input operand is made to stand by at a Reservation Station (which will be referred to as an "RS", corresponding to a queue of the instruction) and is taken into the input operand of the RS through a common data bus CDB, as soon as said arithmetic result is attained, so that the arithmetic is started from the instruction by which all the input operands are defined. In this CDB system, the RS has to be equipped therein with two registers for first and second operands in respect to all the instructions, and the number of the registers takes a value of 2N and the maximum number of the instructions being processed in the system may take a value N, thus presenting a problem that the logical scale has to be enlarged. In case the arithmetic results are attained simultaneously by a plurality of arithmetic units, there arises a problem in that the common data bus CDB has trouble with the transfer of said arithmetic results to a plurality of arithmetic units requiring them.